The present invention relates to digital to analog conversion and, in particular, to cancellation of digital feedthrough.
Many digital to analog conversion (DAC) circuits have issues with unacceptable digital signal interference feeding through to the analog signal. The problem is that a minute amount of capacitance between the digital inputs and the analog outputs can be enough to couple the two.
Typically, DACs operate with a clock input and a data input. A trigger event (e.g., a rising clock edge, a falling clock edge, or both) latches the data input into the DAC. For this data latching to happen, the data is required to be present for a time window between a “setup time” before the trigger event and a “hold time” after the trigger event.
Referring to FIG. 2, an example timing diagram for a parallel-input DAC that uses the rising edge as the trigger event is shown. An example time window A is shown about a rising clock edge.
For example, where a sine wave is being generated, the most significant bit of the data input will have a significant content of the frequency that is being outputted and this content will couple through the capacitance to the analog signal output, corrupting the analog waveform. This is possibly true even for very small signal levels, where the average of the signal is zero and it toggles between positive and negative output.